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DESCRIPTION
The WM8950 is a low power, high quality mono ADC designed for portable applications such as Digital Still Camera, Digital Voice Recorder or games console accessories. The device integrates support for a differential or single ended mic. External component requirements are reduced as no separate microphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation filters to give high quality audio at sample rates from 8 to 48ks/s. Additional digital filtering options are available, to cater for application filtering such as wind noise reduction, noise rejection, plus an advanced mixed signal ALC function with noise gate is provided. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8950 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. Different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. WM8950 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance.
WM8950
ADC with Microphone Input and Programmable Digital Filters
FEATURES
* * * * * * Mono ADC: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz SNR 95dB, THD -85dB (`A'-weighted @ 8 - 48ks/s) Multiple auxiliary analog inputs Mic Preamps: Differential or single end Microphone Interface - Programmable preamp gain - Psuedo differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones
*
OTHER FEATURES * 5 band EQ * Programmable High Pass Filter (wind noise reduction) * Fully Programmable IIR Filter (notch filter) * On-chip PLL * Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) - power consumption TBD all-on 48ks/s mode * 4x4x0.9mm 24 pin QFN package
APPLICATIONS
* * * * Digital Still Camera General Purpose low power audio ADC Games console accessories Voice recorders
WOLFSON MICROELECTRONICS plc
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Preliminary Technical Data, June 2005, Rev 2.1
Copyright 2005 Wolfson Microelectronics plc
WM8950 TABLE OF CONTENTS
Preliminary Technical Data
DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 7
SIGNAL TIMING REQUIREMENTS .......................................................................8
SYSTEM CLOCK TIMING ............................................................................................. 8 AUDIO INTERFACE TIMING - MASTER MODE .......................................................... 8 AUDIO INTERFACE TIMING - SLAVE MODE.............................................................. 9 CONTROL INTERFACE TIMING - 3-WIRE MODE .................................................... 10 CONTROL INTERFACE TIMING - 2-WIRE MODE .................................................... 11
DEVICE DESCRIPTION.......................................................................................12
INTRODUCTION ......................................................................................................... 12 INPUT SIGNAL PATH ................................................................................................. 13 ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 18 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 21 DIGITAL AUDIO INTERFACES................................................................................... 29 AUDIO SAMPLE RATES ............................................................................................. 35 MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 35 GENERAL PURPOSE INPUT/OUTPUT...................................................................... 37 CONTROL INTERFACE.............................................................................................. 38
RESETTING THE CHIP........................................................................................39
POWER SUPPLIES .................................................................................................... 39 POWER MANAGEMENT ............................................................................................ 39
REGISTER MAP...................................................................................................41 DIGITAL FILTER CHARACTERISTICS ...............................................................42
TERMINOLOGY .......................................................................................................... 42
ADC FILTER RESPONSES .................................................................................43
DE-EMPHASIS FILTER RESPONSES........................................................................ 44
HIGHPASS FILTER..............................................................................................45
5-BAND EQUALISER .................................................................................................. 46
APPLICATIONS INFORMATION .........................................................................50
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 50
PACKAGE DIAGRAM ..........................................................................................51 IMPORTANT NOTICE ..........................................................................................52
ADDRESS ................................................................................................................... 52
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Preliminary Technical Data
WM8950
PIN CONFIGURATION
TOP VIEW
ORDERING INFORMATION
ORDER CODE WM8950GEFL/V WM8950GEFL/RV Note: Reel Quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C PACKAGE 24-pin QFN (4x4x0.9mm) (lead free) 24-pin QFN (4x4x0.9mm) (lead free, tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PACKAGE BODY TEMPERATURE 260oC 260oC
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WM8950 PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME MICBIAS AVDD AGND DCVDD DBVDD DGND ADCDAT TP FRAME BCLK MCLK CSB/GPIO SCLK SDIN MODE DNC DNC AGND2 DNC AVDD2 AUX VMID MICN MICP TYPE Analogue Output Supply Supply Supply Supply Supply Digital Output Test Pin Digital Input / Output Digital Input / Output Digital Input Digital Input / Output Digital Input Digital Input / Output Digital Input Do not connect Do not connect Supply Do not connect Supply Analogue Input Reference Analogue Input Analogue Input Microphone bias Analogue supply (feeds ADC) Analogue ground (feeds ADC) Digital core supply Digital buffer (input/output) supply Digital ground ADC digital audio data output Connect to ground ADC sample rate clock or frame synch Digital audio bit clock Master clock input DESCRIPTION
Preliminary Technical Data
3-Wire MPU chip select or general purpose input/output pin. 3-Wire MPU clock Input / 2-Wire MPU Clock Input 3-Wire MPU data Input / 2-Wire MPU Data Input Control interface mode selection pin. Leave this pin floating Leave this pin floating Analogue ground Leave this pin floating Analogue supply Auxiliary analogue input Decoupling for midrail reference voltage Microphone negative input Microphone positive input (common mode)
Note: It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
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Preliminary Technical Data
WM8950
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION DBVDD, DCVDD, AVDD, AVDD2 supply voltages Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature prior to soldering Storage temperature after soldering Notes 1. 2. Analogue and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. MIN -0.3V DGND -0.3V AGND -0.3V -25C -65C MAX +4.2 DVDD +0.3V AVDD +0.3V +85C +150C
30C max / 85% RH max
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range Ground Notes 1. When using PLL, DCVDD must be 1.9V or higher. SYMBOL DCVDD DBVDD AVDD, AVDD2 DGND, AGND, AGND2 TEST CONDITIONS MIN 1.711 1.71 2.5 0 TYP MAX 3.6 3.6 3.6 UNIT V V V V
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WM8950 ELECTRICAL CHARACTERISTICS
Preliminary Technical Data
Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Microphone Inputs (MICN, MICP) Full-scale Input Signal Level (Note 1) - note this changes with AVDD Mic PGA equivalent input noise Input resistance Input resistance Input resistance Input resistance Input resistance Input Capacitance Recommended coupling cap Programmable Gain Programmable Gain Step Size Mute Attenuation Selectable Input Gain Boost (0/+20dB) Gain Boost Automatic Level Control (ALC)/Limiter Target Record Level Programmable Gain Programmable Gain Step Size Gain Hold Time (Note 2) Gain Ramp-Up (Decay) Time (Note 3) tHOLD tDCY Guaranteed Monotonic MCLK=12.288MHz (Note 4) ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Gain Ramp-Down (Attack) Time (Note 3) tATK ALCMODE=0 (ALC), MCLK=12.288MHz (Note 4) ALCMODE=1 (limiter), MCLK=12.288MHz (Note 4) Mute Attenuation Analogue to Digital Converter (ADC) Signal to Noise Ratio (Note 5, 6) Total Harmonic Distortion (Note 6) Auxiliary Analogue Input (AUX) Full-scale Input Signal Level (0dB) - note this changes with AVDD Input Resistance Input Capacitance VINFS RAUXIN CAUXIN AUXMODE=0 1.0 0 20 10 Vrms dBV k pF A-weighted, 0dB gain full-scale, -1dB 95 -85 dB dB -28.5 -12 0.75 0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 3.3, 6.6, 13.1, ... , 3360 (time doubles with each step) 0.73, 1.45, 2.91, ... , 744 (time doubles with each step) 0.83, 1.66, 3.33, ... , 852 (time doubles with each step) 0.18, 0.36, 0.73, ... , 186 (time doubles with each step) TBD dB ms -6 35.25 dB dB dB ms ms 0 20 dB Guaranteed monotonic VINFS PGABOOST = 0dB INPPGAVOL = 0dB 1.0 0 TBD Gain set to 35.25dB Gain set to 0dB Gain set to -12dB MICP2INPPGA = 1 MICP2INPPGA = 0 1.6 47 75 94 TBD 10 220 -12 0.75 TBD 35.25 Vrms dBV uV k k k k k pF pF dB dB dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
At 35.25dB gain RMICIN RMICIN RMICIN RMICIP RMICIP CMICIN CCOUP
MIC Input Programmable Gain Amplifier (PGA)
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Preliminary Technical Data
WM8950
Test Conditions DCVDD = 1.8V, AVDD = DBVDD = 3.3V, SPKVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Microphone Bias Bias Voltage (MBVSEL=0) Bias Voltage (MBVSEL=1) Bias Current Source Output Noise Voltage Digital Input / Output Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level VIH VIL VOH VOL IOL=1mA IOH-1mA 0.9xDVDD 0.1xDVDD 0.7xDVDD 0.3xDVDD V V V V VMICBIAS VMICBIAS IMICBIAS Vn 1K to 20kHz 15 0.9*AVDD 0.75*AVDD 3 V V mA nV/Hz SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
TERMINOLOGY
1. 2. 3. 4. 5. 6. MICN input only in single ended microphone configuration. Maximum input signal to MICP without distortion is -3dBV. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to change it's gain by 6dB. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
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WM8950 SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Preliminary Technical Data
Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock cycle time MCLK duty cycle TMCLKY TMCLKDS Tbd 60:40 40:60 ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface)
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Preliminary Technical Data
WM8950
Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information FRAME propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge tDL tDDA 10 10 ns ns SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - SLAVE MODE
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK= 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK cycle time BCLK pulse width high BCLK pulse width low FRAME set-up time to BCLK rising edge FRAME hold time from BCLK rising edge Note: BCLK period should always be greater than or equal to MCLK period. tBCY tBCH tBCL tLRSU tLRH 50 20 20 10 10 ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8950
CONTROL INTERFACE TIMING - 3-WIRE MODE
Preliminary Technical Data
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tps 80 200 80 80 40 40 40 40 40 0 5 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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Preliminary Technical Data
WM8950
CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t8 t5 t3
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 1.3 600 600 600 100 300 300 526 kHz us ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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WM8950 DEVICE DESCRIPTION
INTRODUCTION
Preliminary Technical Data
The WM8950 is a low power audio ADC, with flexible line and microphone input. Applications for this device include games console accessories, digital still cameras, voice recorders and other general purpose audio applications.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
MICROPHONE INPUTS
Microphone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. These inputs have a user programmable gain range of -12dB to +35.25dB using internal resistors. After the input PGA stage comes a boost stage which can add a further 20dB of gain. A microphone bias is output from the chip which can be used to bias the microphones. The signal routing can be configured to allow manual adjustment of mic levels, or to allow the ALC loop to control the level of mic signal that is transmitted. Total gain through the microphone paths of up to +55.25dB can be selected.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analogue/digital automatic level control (ALC) which keeps the recording volume constant.
AUX INPUT
The device includes a mono input, AUX, that can be used as an input for warning tones (beep) etc. This path can also be summed into the input in a flexible fashion, either to the input PGA as a second microphone input or as a line input. The configuration of this circuit, with integrated on-chip resistors allows several analogue signals to be summed into the single AUX input if required.
ADC
The mono ADC uses a multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice dictation, up to the 48ks/s rate used in high quality audio applications.
DIGITAL FILTERING
Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8ks/s to 48ks/s. Application specific digital filters are also available which help to reduce the effect of specific noise sources such as `wind noise'. The filters include a programmable ADC high pass filter, an IIR filter with fully programmable coefficients, and a 5-band equaliser that can be applied to the record path in order to improve the overall audio sound from the device.
AUDIO INTERFACES
The WM8950 has a standard audio interface, to support the transmission of audio data from the chip. This interface is a 4 wire standard audio interface which supports a number of audio data formats including I2S, DSP Mode, MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes.
CONTROL INTERFACES
To allow full software control over all its features, the WM8950 offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if MODE is low then 2-wire control mode is selected. In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8950 offers the normal audio clocking scheme operation, where 256fs MCLK is provided to the ADC.
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Preliminary Technical Data
WM8950
However, a PLL is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. This PLL uses an input clock, typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the CSB/GPIO pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8950 has given much attention to power consumption without compromising performance. It operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control, includes standby and power off modes.
INPUT SIGNAL PATH
The WM8950 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA block which then feeds into a gain boost/mixer stage.
MICROPHONE INPUTS
The WM8950 can accommodate a variety of microphone configurations including single ended and differential inputs. The inputs through the MICN, MICP and optionally AUX pins are amplified through the input PGA as shown in Figure 6 . A pseudo differential input is the preferential configuration where the positive terminal of the input PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when AUX2INPPGA=1) input pins. Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting MICP2INPPGA to 0.
Figure 6 Microphone Input PGA Circuit (switch positions shown are for differential mic input)
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WM8950
REGISTER ADDRESS R44 Input Control BIT 0 LABEL MICP2INPPGA 1 DEFAULT
Preliminary Technical Data
DESCRIPTION Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal.
1
MICN2INPPGA
1
2
AUX2INPPGA
0
The input PGA is enabled by the IPPGAEN register bit. REGISTER ADDRESS R2 Power Management 2 2 BIT LABEL INPPGAEN DEFAULT 0 DESCRIPTION Input microphone PGA enable 0 = disabled 1 = enabled
INPUT PGA VOLUME CONTROL
The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain from the MICN input to the PGA output and from the AUX amplifier to the PGA output are always common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the MICP pin when MICP2INPPGA=1. When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled automatically and the INPPGAVOL bits should not be used. REGISTER ADDRESS R45 Input PGA volume control BIT 5:0 LABEL INPPGAVOL DEFAULT 010000 DESCRIPTION Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain)
6
INPPGAMUTE
0
7
INPPGAZC
0
R32 8 ALC control 1
ALCSEL
0
Table 1 Input PGA Volume Control
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Preliminary Technical Data
WM8950
AUXILIARY INPUT
An auxiliary input circuit (Figure 7) is provided which consists of an amplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. The circuit is enabled by the register bit AUXEN.
Figure 7 Auxiliary Input Circuit The AUXMODE register bit controls the auxillary input mode of operation: In buffer mode (AUXMODE=0) the switch labelled AUXSW in Figure 7 is open and the signal at the AUX pin will be buffered and inverted through the aux circuit using only the internal components. In mixer mode (AUXMODE=1) the on-chip input resistor is bypassed, this allows the user to sum in multiple inputs with the use of external resistors. When used in this mode there will be gain variations through this path from part to part due to the variation of the internal 20k resistors relative to the higher tolerance external resistors. REGISTER ADDRESS R1 Power management 1 R44 Input control 6 BIT LABEL AUXEN DEFAULT 0 DESCRIPTION Auxiliary input buffer enable 0 = OFF 1 = ON 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed)
3
AUXMODE
0
Table 2 Auxiliary Input Buffer Control
INPUT BOOST
The input BOOST circuit has 3 selectable inputs: the input microphone PGA output, the AUX amplifier output and the MICP input pin (when not using a differential microphone configuration). These three inputs can be mixed together and have individual gain boost/adjust as shown in Figure 8.
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WM8950
Preliminary Technical Data
Figure 8 Input Boost Stage The input PGA path can have a +20dB boost (PGABOOST=1) a 0dB pass through (PGABOOST=0) or be completely isolated from the input boost circuit (INPPGAMUTE=1). REGISTER ADDRESS 6 R45 Input PGA gain control R47 Input BOOST control 8 BIT LABEL INPPGAMUTE DEFAULT 0 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage.
PGABOOST
1
Table 3 Input BOOST Stage Control The Auxiliary amplifier path to the BOOST stage is controlled by the AUX2BOOSTVOL[2:0] register bits. When AUX2BOOSTVOL=000 this path is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. The MICP path to the BOOST stage is controlled by the MICP2BOOSTVOL[2:0] register bits. When MICP2BOOSTVOL=000 this input pin is completely disconnected from the BOOST stage. Settings 001 through to 111 control the gain in 3dB steps from -12dB to +6dB. REGISTER ADDRESS R47 Input BOOST control BIT 2:0 LABEL AUX2BOOSTVOL DEFAULT 000 DESCRIPTION Controls the auxiliary amplifer to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage Controls the MICP pin to the input boost stage (NB, when using this path set MICPZIUNPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage ... 111=+6dB gain through boost stage
6:4
MICP2BOOSTVOL
000
Table 4 Input BOOST Stage Control
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Preliminary Technical Data The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 BIT 4 LABEL BOOSTEN DEFAULT 0 DESCRIPTION Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON
WM8950
Table 5 Input BOOST Enable Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.75*AVDD. The output can be enabled or disabled using the MICBEN control bit. REGISTER ADDRESS R1 Power management 1 4 BIT LABEL MICBEN DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 6 Microphone Bias Enable
REGISTER ADDRESS R44 Input Control 8
BIT
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD
Table 7 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 9. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
VMID internal resistor
MB
MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD MBVSEL=1 MICBIAS = 1.5 x VMID = 0.75 X AVDD
internal resistor
AGND
Figure 9 Microphone Bias Schematic
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WM8950
ANALOGUE TO DIGITAL CONVERTER (ADC)
Preliminary Technical Data
The WM8950 uses a multi-bit, oversampled sigma-delta ADC channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms. Any voltage greater than -1dBfs may overload the ADC and cause distortion.
ADC DIGITAL FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in Figure 10 .
Figure 10 ADC Digital Filter Path
The ADC is enabled by the ADCEN register bit. REGISTER ADDRESS R2 Power management 2 Table 8 ADC Enable The polarity of the output signal can also be changed under software control using the ADCPOL register bit. The oversampling rate of the ADC can be adjusted using the ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power operation and when ADCOSR=1 the oversample rate is 128x which gives best performance. REGISTER ADDRESS R14 ADC Control 3 BIT LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversample rate select: 0=64x (lower power) 1=128x (best performance) 0=normal 1=inverted 0 BIT LABEL ADCEN DEFAULT 0 DESCRIPTION 0 = ADC disabled 1 = ADC enabled
0
ADCPOL
0
Table 9 ADC Oversample Rate Select
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Preliminary Technical Data
WM8950
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown in Table 11. REGISTER ADDRESS R14 ADC Control 8 BIT LABEL HPFEN DEFAULT 1 DESCRIPTION High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 11 for details.
7
HPFAPP
0
6:4 Table 10 ADC Filter Select
HPFCUT
000
HPFCUT [2:0]
SAMPLE FREQUENCY (kHz) 8 11.025 SR=101/100 12 16 22.05 SR=011/010 122 153 156 245 306 392 490 612 82 102 131 163 204 261 327 408 113 141 180 225 281 360 450 563 122 153 156 245 306 392 490 612 82 102 131 163 204 261 327 408 24 32 44.1 SR=001/000 113 141 180 225 281 360 450 563 122 153 156 245 306 392 490 612 48
000 001 010 011 100 101 110 111
82 102 131 163 204 261 327 408
113 141 180 225 281 360 450 563
Table 11 High Pass Filter Cut-off Frequencies (HPFAPP=1) Values in Hz Note that the High Pass filter values (when HPFAPP=1) work on the basis that the SR register bits are set correctly for the actual sample rate as shown in Table 11.
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PROGRAMMABLE IIR FILTER
Preliminary Technical Data
An IIR filter with fully programmable coefficients is provided, typically used as a notch filter for removing narrow band noise at a given frequency. This notch filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits NFA0[13:0] and NFA1[13:0]. Because these coefficient values require four register writes to setup there is an NFU (Notch Filter Update) flag which should be set only when all four registers are setup. REGISTER ADDRESS R27 Notch Filter 1 7 BIT 6:0 LABEL NFA0[13:7] NFEN DEFAULT 0 0 DESCRIPTION Notch Filter a0 coefficient, bits [13:7] Notch filter enable: 0=Disabled 1=Enabled Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a0 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Notch Filter a1 coefficient, bits [13:7] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. R30 Notch Filter 4 6:0 8 NFA1[6:0] NFU 0 0 Notch Filter a1 coefficient, bits [6:0] Notch filter update. The notch filter values used internally only update when one of the NFU bits is set high. Table 12 Notch Filter Function The coefficients are calculated as follows:
8
NFU
0
R28 Notch Filter 2
6:0 8
NFA0[6:0] NFU]
0 0
R29 Notch Filter 3
6:0 8
NFA1[13:7] NFU
0 0
a0 =
1 - tan( wb / 2) 1 + tan( wb / 2)
a1 = -(1 + a0 ) cos(w0 )
Where:
w0 = 2f c / f s wb = 2f b / f s
fc = centre frequency in Hz, fb = -3dB bandwidth in Hz, fs = sample frequency in Hz The actual register values can be determined from the coefficients as follows: NFA0 = -a0 x 213 NFA1 = -a1 x 212
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Preliminary Technical Data
WM8950
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally attenuated over a range from -127dB to 0dB in 0.5dB steps. The gain for a given eight-bit code X is given by: Gain = 0.5 x (x-255) dB for 1 x 255, MUTE for x = 0 REGISTER ADDRESS R15 ADC Digital Volume BIT 7:0 LABEL ADCVOL [7:0] DEFAULT 11111111 ( 0dB ) DESCRIPTION ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB
Table 13 ADC Volume
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
The WM8950 has an automatic pga gain control circuit, which can function as an input peak limiter or as an automatic level control (ALC). In input peak limiter mode (ALCMODE bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. The peak limiter cannot increase the pga gain above its static level.
Figure 11 Input Peak Limiter Operation In ALC mode (ALCMODE bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
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WM8950
Preliminary Technical Data
Figure 12 ALC Operation The ALC/Limiter function is enabled by setting the register bit ALCSEL. When enabled, the recording volume can be programmed between -6dB and -28.5dB (relative to ADC full scale) using the ALCLVL register bits. An upper limit for the PGA gain can be imposed by setting the ALCMAX control bits and a lower limit for the PGA gain can be imposed by setting the ALCMIN control bits. ALCHLD, ALCDCY and ALCATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time is not active in limiter mode (ALCMODE = 1). The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up and is given as a time per gain step, time per 6dB change and time to ramp up over 90% of it's range. The decay time can be programmed in power-of-two (2n) steps, from 3.3ms/6dB, 6.6ms/6dB, 13.1ms/6dB, etc. to 3.36s/6dB. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down and is given as a time per gain step, time per 6dB change and time to ramp down over 90% of it's range. The attack time can be programmed in power-of-two (2n) steps, from 832us/6dB, 1.66ms/6dB, 3.328us/6dB, etc. to 852ms/6dB. NB, In peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. Attack and Decay times for peak limiter mode are given below. The hold, decay and attack times given in Table 14 are constant across sample rates so long as the SR bits are set correctly. E.g. when sampling at 48kHz the sample rates stated in Table 14 will only be correct if the SR bits are set to 000 (48kHz). If the actual sample rate was only 44.1kHz then the hold, decay and attack times would be scaled down by 44.1/48.
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Preliminary Technical Data
WM8950
REGISTER ADDRESS R32 8 ALC Control 1 5:3 BIT LABEL ALCSEL 0 DEFAULT DESCRIPTION ALC function select 0=ALC disabled 1=ALC enabled Set Maximum Gain of PGA 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC target - sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS ... (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS
ALCMAXGAIN 111 (+35.25dB) [2:0]
2:0
ALCMINGAIN [2:0]
000 (-12dB)
R33 7:4 ALC Control 2
ALCHLD [3:0]
0000 (0ms)
3:0
ALCLVL [3:0]
1011 (-12dB)
8
ALCZC
0 (zero cross ALC uses zero cross detection circuit. off)
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R34 8 ALC Control 3 7:4 ALCMODE 0
Preliminary Technical Data Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode. Decay (gain ramp-up) time (ALCMODE =0) Per step 0000 0001 0010 1010 or higher 0011 (2.9ms/6dB) 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s
ALCDCY [3:0]
0011 (13ms/6dB)
... (time doubles with every step)
Decay (gain ramp-up) time (ALCMODE =1) Per step 0000 0001 0010 1010 90.8us 181.6us 363.2us 93ms Per 6dB 726.4us 1.453ms 2.905ms 744ms 90% of range 5.26ms 10.53ms 21.06ms 5.39s
... (time doubles with every step) 3:0 ALCATK [3:0] 0010 (832us/6dB) ALC attack (gain ramp-down) time (ALCMODE = 0) Per step 0000 0001 0010 1010 or higher 0010 (182us/6dB) 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s
... (time doubles with every step)
ALC attack (gain ramp-down) time (ALCMODE = 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s
... (time doubles with every step) Table 14 ALC Control Registers
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Preliminary Technical Data
WM8950
ALC CLIP PROTECTION
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a clip protection function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ALCATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: If ATK = 0000, then the clip protection circuit makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8950 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The PGA gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. Note that the noise gate only works in conjunction with the ALC function. REGISTER ADDRESS R35 ALC Noise Gate Control BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION Noise gate threshold: 000=-39dB 001=-45dB 010=-51db ... (6dB steps) 111=-81dB Noise gate function enable 1 = enable 0 = disable
3
NGATEN
0
Table 15 ALC Noise Gate Control
GRAPHIC EQUALISER
A 5-band graphic EQ is provided, which can be applied to the ADC data under control of the EQMODE register bit. REGISTER ADDRESS R18 EQ Control 1 8 BIT LABEL EQMODE 1 DEFAULT DESCRIPTION 0 = Equaliser applied to ADC data 1 = Equaliser bypassed
Table 16 EQ Select
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Preliminary Technical Data The equaliser consists of low and high frequency shelving filters (Band 1 and 5) and three peak filters for the centre bands. Each has adjustable cut-off or centre frequency, and selectable boost (+/- 12dB in 1dB steps). The peak filters have selectable bandwidth.
REGISTER ADDRESS R18 EQ Band 1 Control
BIT 4:0 6:5
LABEL EQ1G EQ1C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 1 Gain Control. See Table 22 for details. Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz
Table 17 EQ Band 1 Control
REGISTER ADDRESS R19 EQ Band 2 Control
BIT 4:0 6:5
LABEL EQ2G EQ2C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 2 Gain Control. See Table 22 for details. Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz
8
EQ2BW
0
11=500Hz Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
Table 18 EQ Band 2 Control
REGISTER ADDRESS R20 EQ Band 3 Control
BIT 4:0 6:5
LABEL EQ3G EQ3C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 3 Gain Control. See Table 22 for details. Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz
8
EQ3BW
0
11=1.4kHz Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
Table 19 EQ Band 3 Control
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Preliminary Technical Data
WM8950
REGISTER ADDRESS R21 EQ Band 4 Control BIT 4:0 6:5 LABEL EQ4G EQ4C DEFAULT 01100 (0dB) 01 DESCRIPTION Band 4 Gain Control. See Table 22 for details Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth
8
EQ4BW
0
Table 20 EQ Band 4 Control
REGISTER ADDRESS R22 EQ Band 5 Gain Control
BIT 4:0 6:5
LABEL EQ5G EQ5C
DEFAULT 01100 (0dB) 01
DESCRIPTION Band 5 Gain Control. See Table 22 for details. Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz
Table 21 EQ Band 5 Control
GAIN REGISTER 00000 00001 00010 .... (1dB steps) 01100 01101 11000 to 11111 Table 22 Gain Register Table
GAIN +12dB +11dB +10dB 0dB -1dB -12dB
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Preliminary Technical Data
A dedicated buffer is available for tieing off unused analogue input pins as shown below Figure 13. This buffer can be enabled using the BUFIOEN register bit.
Figure 13 Unused Input Pin Tie-off Buffers
THERMAL SHUTDOWN
To protect the WM8950 from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 1250C and the thermal shutdown circuit is enabled (TSDEN=1), an interrupt can be generated. See the GPIO and Interrupt Controller section for details.
REGISTER ADDRESS R49 Output control 1
BIT
LABEL TSDEN 1
DEFAULT
DESCRIPTION Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled
Table 23 Thermal Shutdown
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Preliminary Technical Data
WM8950
The audio interface has three pins: * * * ADCDAT: ADC data output FRAME: Data alignment clock BCLK: Bit clock, for synchronisation
DIGITAL AUDIO INTERFACES
The clock signals BCLK, and FRAME can be outputs when the WM8950 operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). Five different audio data formats are supported: * * * * * Left justified Right justified I 2S DSP mode early DSP mode late
All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8950 audio interface may be configured as either master or slave. As a master interface device the WM8950 generates BCLK and FRAME and thus controls sequencing of the data transfer on ADCDAT. To set the device to master mode register bit MS should be set high. In slave mode (MS=0), the WM8950 responds with data to clocks it receives over the digital audio interfaces.
AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.
Figure 14 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.
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Preliminary Technical Data
Figure 15 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
Figure 16 I2S Audio Interface (assuming n-bit word length) In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 17 and Figure 18. In device slave mode, Figure 19 and Figure 20, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse.
Figure 17 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master)
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WM8950
Figure 18 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master)
Figure 19 DSP/PCM Mode Audio Interface (mode A, LRP=0, Slave)
Figure 20 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave)
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Preliminary Technical Data
When using ADCLRSWAP = 1 in DSP/PCM mode, the data will appear in the Right Phase of the FRAME, which will be 16/20/24/32 bits after the FRAME pulse.
REGISTER ADDRESS R4 Audio interface control 1
BIT
LABEL ADCLRSWAP
DEFAULT 0
DESCRIPTION Controls whether ADC data appears in `right' or `left' phases of FRAME clock: 0=ADC data appear in `left' phase of FRAME 1=ADC data appears in `right' phase of FRAME Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) Frame clock polarity 0=normal 1=inverted DSP Mode - mode A/B select 1 = MSB is available on 1st BCLK rising edge after FRAME rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after FRAME rising edge (mode A)
4:3
FMT
10
6:5
WL
10
7
FRAMEP
0
8
BCP
0
BCLK polarity 0=normal 1=inverted
Table 24 Audio Interface Control
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. Register bit MS selects audio interface operation in master or slave mode. In Master mode BCLK, and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.
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Preliminary Technical Data
WM8950
REGISTER ADDRESS R6 Clock generation control 0 BIT MS LABEL DEFAULT 0 DESCRIPTION Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8950 (MASTER) Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output
4:2
BCLKDIV
000
7:5
MCLKDIV
010
8
CLKSEL
1
Table 25 Clock Control
COMPANDING
The WM8950 supports A-law and -law companding. Companding can be enabled on the ADC audio interface by writing the appropriate value to the ADC_COMP register bit.
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REGISTER ADDRESS R5 Companding control BIT 2:1 LABEL ADC_COMP DEFAULT 0
Preliminary Technical Data
DESCRIPTION ADC companding 00=off 01=reserved 10=-law 11=A-law
Table 26 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: -law (where =255 for the U.S. and Japan): F(x) = ln( 1 + |x|) / ln( 1 + ) A-law (where A=87.6 for Europe): F(x) = A|x| / ( 1 + lnA) F(x) = ( 1 + lnA|x|) / (1 + lnA) } for x } for 1/A 1/A x 1 -1 x 1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB's of data. Companding converts 13 bits (-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. This is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).
BIT8 SIGN
BIT[7:4] EXPONENT
BIT[3:0] MANTISSA
Table 27 8-bit Companded Word Composition
u-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 21 u-Law Companding
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Preliminary Technical Data
WM8950
A-law Companding
1 120 100 Companded Output 80 60 40 20 0 0 0.2 0.4 0.6 0.8 1 Normalised Input 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Normalised Output
Figure 22 A-Law Companding
AUDIO SAMPLE RATES
The WM8950 sample rate for the ADC is set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and assume a 256fs master clock rate. If a sample rate that is not explicitly supported by the SR register settings is required then the closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack, decay and hold times will scale appropriately. REGISTER ADDRESS R7 Additional control BIT 3:1 SR LABEL DEFAULT 000 DESCRIPTION Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved
Table 28 Sample Rate Control
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
The WM8950 has an on-chip phase-locked loop (PLL) circuit that can be used to: Generate master clocks for the WM8950 audio functions from another external clock, e.g. in telecoms applications. Generate and output (on pin CSB/GPIO) a clock for another part of the system that is derived from an existing audio master clock. Figure 23 shows the PLL and internal clocking arrangment on the WM8950. The PLL can be enabled or disabled by the PLLEN register bit.
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REGISTER ADDRESS R1 Power management 1 5 BIT LABEL PLLEN DEFAULT 0 PLL enable 0=PLL off 1=PLL on
Preliminary Technical Data
DESCRIPTION
Table 29 PLLEN Control Bit
Figure 23 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 23) can be set using the register bits PLLK and PLLN: PLLN = int R PLLK = int (2 EXAMPLE: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement. Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 PLLN = int R = 8 k = int ( 224 x (8.192 - 8)) = 3221225 = 3126E9h REGISTER ADDRESS R36 PLL N value 4 3:0 BIT LABEL PLLPRESCALE PLLN DEFAULT 0 1000 DESCRIPTION Divide MCLK by 2 before input to PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number).
24
(R-PLLN))
R37 PLL K value 1 R38 PLL K Value 2 R39 PLL K Value 3
5:0 8:0 8:0
PLLK [23:18] PLLK [17:9] PLLK [8:0]
0Ch 093h 0E9h
Table 30 PLL Frequency Ratio Control
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Preliminary Technical Data
WM8950
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown in Table 31. MCLK (MHz) (F1) 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 11.29 12.288 F2 (MHz) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 PRESCALE POSTSCALE DIVIDE DIVIDE 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R N (Hex) 7.5264 8.192 6.947446 7.561846 6.272 6.826667 9.408 10.24 9.178537 9.990243 9.122909 9.929697 7.5264 8.192 6.947446 7.561846 6.690133 7.281778 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7 K (Hex) 86C227 3126E9 F28BD5 8FD526 45A1CB D3A06D 6872B0 3D70A4 2DB493 FD80A0 1F76F8 EE009F 86C227 3126E9 F28BD5 8FD526 BOAC94 482297
Table 31 PLL Frequency Examples
GENERAL PURPOSE INPUT/OUTPUT
The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL register bits. The GPIO is only available in 2 wire mode. REGISTER ADDRESS R8 GPIO control BIT 2:0 LABEL GPIOSEL DEFAULT 000 DESCRIPTION CSB/GPIO pin function select: 000=CSB input 001=Reserved 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved GPIO Polarity invert 0=Non inverted 1=Inverted PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4
3
GPIOPOL
0
5:4
OPCLKDIV
00
Table 32 CSB/GPIO Control
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CONTROL INTERFACE
Preliminary Technical Data
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the 2 or 3 wire mode as shown in Table 33. The WM8950 is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register. MODE Low High INTERFACE FORMAT 2 wire 3 wire
Table 33 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on CSB/GPIO latches in a complete control word consisting of the last 16 bits.
Figure 24 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8950 supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8950). The WM8950 operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8950, then the WM8950 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8950 returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8950 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8950 register address plus the first bit of register data). The WM8950 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8950 acknowledges again by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8950 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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Preliminary Technical Data
WM8950
SDIN DEVICE ADDRESS (7 BITS) RD / WR BIT ACK (LOW) CONTROL BYTE 1 (BITS 15 TO 8) ACK (LOW) CONTROL BYTE 1 (BITS 7 TO 0) ACK (LOW)
SCLK
START
register address and 1st register data bit
remaining 8 bits of register data
STOP
Figure 25 2-Wire Serial Control Interface In 2-wire mode the WM8950 has a fixed device address, 0011010.
RESETTING THE CHIP
The WM8950 can be reset by performing a write of any value to the software reset register (address 0 hex). This will cause all register values to be reset to their default values. In addition to this there is a Power-On Reset (POR) circuit which ensures that the registers are set to default when the device is powered up.
POWER SUPPLIES
The WM8950 can use up to three separate power supplies: AVDD, AVDD2, AGND and AGND2: Analogue supply, powers all analogue functions. AVDD can range from 2.5V to 3.6V and has the most significant impact on overall power consumption. A large AVDD slightly improves audio quality. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.71V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD Can range from 1.71V to 3.6V. DBVDD return path is through DGND. It is possible to use the same supply voltage for all supplies. However, digital and analogue supplies should be routed and decoupled separately on the PCB to keep digital switching noise out of the analogue signal paths.
POWER MANAGEMENT
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC digital filters is in 64x oversampling mode. Under the control of ADCOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. REGISTER ADDRESS R14 ADC control 3 BIT LABEL ADCOSR128 0 DEFAULT DESCRIPTION ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR)
Table 34 ADC Oversampling Rate Selection
VMID
The analogue circuitry will not work unless VMID is enabled (VMIDSEL 00). The impedance of the VMID resistor string, together with the decoupling capacitor on the VMID pin will determine the startup time of the VMID circuit. REGISTER ADDRESS R1 Power management 1 BIT 1:0 LABEL DEFAULT DESCRIPTION Reference string impedance to VMID pin (detemines startup time): 00=off (open circuit) 01=75k 10=300k 11=2.5k (for fastest startup)
VMIDSEL 00
Table 35 VMID Impedance Control
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WM8950
BIASEN
REGISTER ADDRESS R1 Power management 1 3 BIT LABEL BIASEN DEFAULT 0
Preliminary Technical Data
DESCRIPTION Analogue amplifier bias control
Table 36 BIASEN Control
ESTIMATED SUPPLY CURRENTS
When the ADC is enabled it is estimated that approximately 4mA will be drawn from DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD.
Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT BUFDCOPEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL INPPGAEN ADCEN 0.1 1.4 (with clocks applied) 0.5 0.3 0.1 10K=>0.3, less than 0.1 for 100k/500k 0.2 x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9 AVDD CURRENT (MILLIAMPS)
Table 37 AVDD Supply Current
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Preliminary Technical Data
WM8950
REGISTER MAP
ADDR B[15:9]
DEC HEX
REGISTER NAME Software Reset Power manage't 1 Power manage't 2 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO Stuff DAC Control ADC Control ADC Digital Vol EQ1 - low shelf EQ2 - peak 1 EQ3 - peak 2 EQ4 - peak 3 EQ5 - high shelf Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 Input ctrl INP PGA gain ctrl ADC Boost ctrl Thermal Shutdown
B8
B7
B6
B5
B4
B3
B2
B1
B0
DEF'T VAL (HEX)
0 1 2 4 5 6 7 8 10 14 15 18 19 20 21 22 27 28 29 30 32 33 34 35 36 37 38 39 44 45 47 49
00 01 02 04 05 06 07 08 0A 0E 0F 12 13 14 15 16 1B 1C 1D 1E 20 21 22 23 24 25 26 27 2C 2D 2F 31
Software reset BUFDCOP EN 0 BCP 0 CLKSEL 0 0 0 HPFEN 0 0 EQ2BW EQ3BW EQ4BW 0 NFU NFU NFU NFU ALCSEL ALCZC ALCMODE 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] MBVSEL 0 PGABOOST 0 0 INPPGAZC 0 0 0 0 INPPGA MUTE MICP2BOOSTVOL 0 0 0 0 AUXMODE AUX2 INPPGA MICN2 INPPGA MICP2 INPPGA 0 0 0 0 0 NFEN 0 0 0 0 0 ALCHLD ALCDCY 0 0 0 PLL_PRE SCALE PLLK[23:18] NGEN ALCMAX EQ1C EQ2C EQ3C EQ4C EQ5C NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMIN ALCLVL ALCATK NGTH PLLN[3:0] 0 0 0 HPFAPP 0 0 FRAMEP 0 0 MCLKDIV 0 0 0 0 0 GPIOPOL 0 ADCOSR 128 ADCVOL EQ1G EQ2G EQ3G EQ4G EQ5G AMUTE 0 AUXEN 0 WL 0 PLLEN 0 MICBEN BOOSTEN FMT 0 BCLKDIV SR GPIOSEL 0 0 0 ADCPOL BIASEN 0 BUFIOEN INPPGAEN 0 0 ALRSWAP 0 VMIDSEL ADCEN 0 0 MS SLOWCLK EN 000 000 050 000 140 000 000 000 100 0FF 12C 02C 02C 02C 02C 000 000 000 000 038 00B 032 000 008 00C 093 0E9 003 010 AUX2BOOSTVOL 0 TSDEN 0 100 002
ADC_COMP
OPCLKDIV DEEMPH HPFCUT
INPPGAVOL 0 0
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WM8950 DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB Table 38 Digital Filter Characteristics 3.7 10.4 21.6 f > 0.546fs 0.546fs -60 21/fs +/- 0.025dB -6dB 0 0.5fs TEST CONDITIONS MIN TYP
Preliminary Technical Data
MAX 0.454fs +/- 0.025
UNIT
dB dB
Hz
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
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Preliminary Technical Data
WM8950
ADC FILTER RESPONSES
0.2
0 -20 Response (dB)
Response (dB)
0.15 0.1 0.05 0 -0.05 -0.1
-40 -60 -80 -100 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 26 ADC Digital Filter Frequency Response
Figure 27 ADC Digital Filter Ripple
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WM8950
DE-EMPHASIS FILTER RESPONSES
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
Preliminary Technical Data
0.30 0.25 0.20 Response (dB) 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz)
Figure 28 De-emphasis Frequency Response (32kHz)
Figure 29 De-emphasis Error (32kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 5000 10000 Frequency (Hz) 15000 20000
Figure 30 De-emphasis Frequency Response (44.1kHz)
0 -1 -2 -3 Response (dB) -4 -5 -6 -7 -8 -9 -10 0 5000 10000 Frequency (Hz) 15000 20000
Response (dB)
Figure 31 De-emphasis Error (44.1kHz)
0.10 0.08 0.06 0.04 Response (dB) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 5000 10000 Frequency (Hz) 15000 20000
Figure 32 De-emphasis Frequency Response (48kHz)
Figure 33 De-emphasis Error (48kHz)
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Preliminary Technical Data
WM8950
HIGHPASS FILTER
The WM8950 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cutoff of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cutoff frequency.
5 0 -5 -10 Response (dB)
10 0 -10 Response (dB)
0 5 10 15 20 25 30 35 40 45 Frequency (Hz)
-15 -20 -25 -30 -35 -40
-20 -30 -40 -50 -60 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 34 ADC Highpass Filter Response, HPFAPP=0
Figure 35 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cutoff settings shown.
10 0 -10 -20 Response (dB) -30 -40 -50 -60 -70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200
Response (dB)
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200
Figure 36 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cutoff settings shown.
Figure 37 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cutoff settings shown.
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WM8950
5-BAND EQUALISER
Preliminary Technical Data
The WM8950 has a 5-band equaliser which can be applied to the ADC path. The plots from Figure 38 to Figure 51 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of 12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter.
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 38 EQ Band 1 - Low Frequency Shelf Filter Cut-offs Figure 39 EQ Band 1 - Gains for Lowest Cut-off Frequency
15
15
10
10
5 Magnitude (dB)
5 Magnitude (dB)
0 1 2 3 4 5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 40 EQ Band 2 - Peak Filter Centre Frequencies, EQ2BW=0
15
Figure 41 EQ Band 2 - Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 42 EQ Band 2 - EQ2BW=0, EQ2BW=1
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Preliminary Technical Data
WM8950
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 43 EQ Band 3 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 44 EQ Band 3 - Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 45
EQ Band 3 - EQ3BW=0, EQ3BW=1
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WM8950
Preliminary Technical Data
15
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 46 EQ Band 4 - Peak Filter Centre Frequencies, EQ3BW=0
15
Figure 47 EQ Band 4 - Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0
10
5 Magnitude (dB)
0
-5
-10
-15 -2 10
10
-1
10
0
10 Frequency (Hz)
1
10
2
10
3
10
4
Figure 48
15
EQ Band 4 - EQ3BW=0, EQ3BW=1
15
10
10
5 Magnitude (dB) Magnitude (dB)
0 1 2 3 4 5
5
0
0
-5
-5
-10
-10
-15 -1 10
10
10
10 Frequency (Hz)
10
10
10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 49
EQ Band 5 - High Frequency Shelf Filter Cut-offsFigure 50
EQ Band 5 - Gains for Lowest Cut-off Frequency
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Preliminary Technical Data
WM8950
Figure 51 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with 12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EQxBW=0 for the peak filters.
20
15
10
Magnitude (dB)
5
0
-5
-10
-15 -1 10
10
0
10
1
10 Frequency (Hz)
2
10
3
10
4
10
5
Figure 51
Cumulative Frequency Boost/Cut
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WM8950 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Preliminary Technical Data
Figure 52
Recommended External Components
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Preliminary Technical Data
WM8950
PACKAGE DIAGRAM
FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DETAIL 1
D2 19 24 D
DM035.C
18 EXPOSED GROUND 6 PADDLE A
1 4 E2 INDEX AREA (D/2 X E/2) E
SEE DETAIL 2 13 6 2X 12 e 7 b 1 bbbM C A B 2X aaa C aaa C
TOP VIEW
BOTTOM VIEW
ccc C A3 A 0.08 C 5
DETAIL 1
DETAIL 2
45 degrees
L
1
C
SEATING PLANE
SIDE VIEW
A1
L1 Datum
DETAIL 2
0.32mm EXPOSED GROUND PADDLE e R
Terminal tip e/2
W T A3 H b Exposed lead G
Half etch tie bar
DETAIL 2
Symbols A A1 A3 b D D2 E E2 e G H L L1 T W aaa bbb ccc REF: MIN 0.80 0 0.18 2.00 2.00
Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.20 REF 1 0.30 0.25 4.00 2.15 4.00 2.15 0.50 BSC 0.213 0.1 0.40 0.1 0.2 2.25 2.25 2 2
0.30 0.03
0.50 0.15
7
Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-2.
NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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WM8950 IMPORTANT NOTICE
Preliminary Technical Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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